| 摘要 |
PURPOSE:To contrive the improvement of the reliability of data transmission by stopping a check data in sending a serial data having an error so as to handle it as a conversion error of a reception data. CONSTITUTION:Even when a PS conversion circuit 3 malfunctions due to noise or the like and applies erroneous parallel/serial conversion, an SP conversion circuit 10 receiving an output of the PS conversion circuit 3 and applying the SP conversion converts a serial data converted actually into a parallel data and the data is compared with an output of the latch circuit 2 latching the parallel data obtained in this way in the comparator 11. Thus, whether or not the read parallel data from the storage element 1 is converted serially normally is discriminated. In the case of error conversion, the comparator 11 outputs a noncoincidence signal to a CRC bit generating circuit 4 to stop the production and transmission of a CRC bit. Thus, a serial data transmission control circuit inhibiting the access of a CPU with high reliability is obtained. |
