| 摘要 |
PURPOSE:To obtain a stable shift operation, by setting the channel length of a field effect transistor which constitutes a first inverter larger than that of the field effect transistor which generates a negative phase signal. CONSTITUTION:A reference clock signal phi changes from 0 to 1 at a time t1, and the negative phase signal, the inverse of phi from 1 to 0 at a time t2, and the signal phi from 1 to 0 at a time t3, and the signal, the inverse of phi from 0 to 1 at a time t4, respectively. At this time, since an NEIGFETQN21 is turned ON at the time t1, a point A changes from 0 to 1 at the time t1, however, since the channel length of an NEIGFETQN31 and an NDIGFETQD31 are set larger than those of an NEIGFETQN11 and an NDIGFETQD11, a time when a point B changes from 1 to 0 is delayed than the time t2. Therefore, the logic value of a point C does not change at the time t2, and changes from 1 to 0 at the time t4 when the NEIGFET is turned ON again. As a result, an output O changes from 0 to 1 later than the time t4. In such a way, it is possible to constitute a stable shift register. |
