| 摘要 |
PURPOSE:To have a phase margin in case of executing the conversion of velocity by selecting either a feedback input from a latch circuit or a new input by a selector and converting into a sampling rate. CONSTITUTION:When a selective signal (output Q') is in high level, the selector 25 selects and derives an An input. At a timing X, data D' is outputted and latched in a latch circuit 27. After that, the selective signal (output Q' of a latch circuit 42) becomes in low level and the selector 25 selects a B input. And at the timing Y the latch circuit 27 latches the data D' again. An output from the latch circuit 27 is latched by the latch circuit 29 which is driven with the output Q' of the latch circuit 42. The output from the latch circuit 26 and the output from the latch circuit 29 are respectively supplied to the A input terminal and the B input terminal of a selector 32 after executing specified processes by signal process circuits 30 and 31.
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