DYNAMICALLY ASSIGNABLE SHARED REGISTER SETS

摘要

Dynamic assignment of shared register sets (22) to multiple processors (12) executing a machine instruction sequence (14), is made possible by storing status information (40) that indicates which register sets (22) are assigned to which processors (12), and by including (in the machine instruction sequence (14)) assignment instructions that cause the processors (12) to assign the register sets (22) to the processors (12) based on the status information (40), without interrupting the execution of instructions in the sequence.