发明名称 Circuit arrangement for clearing faults in digital circuits
摘要 When digital circuits process digital signals, surge-like current loads occur which can lead to malfunctions of the circuit. To reduce the surge-like current loads, it is proposed to provide within small circuit board areas an arrangement (6) which processes the signals in parallel by means of complementary logic and thus leads to a uniform current loading. <IMAGE>
申请公布号 DE3709454(A1) 申请公布日期 1988.10.06
申请号 DE19873709454 申请日期 1987.03.23
申请人 SIEMENS AG 发明人 KUNY,WILHELM
分类号 H03K19/003;(IPC1-7):H03K19/003 主分类号 H03K19/003
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