| 摘要 |
PURPOSE:To ensure the fast processing with full adders of a higher rank digit by bypassing the carry signals outputted from a full adder of lower rank digits by an amount equal to the full addition of the prescribed number of digits and giving these carry signals to a full adder of higher rank digits at a high speed in case many prescribed full adders connected in parallel output no carry signal. CONSTITUTION:The carries produced from full adders 1, 3 and 5 connected in parallel with each other in response to the addition information are transmitted to a local carry line LC15. The transfer gates 21 are provided to the line 15 in response to the adders 1-5 so that the carriers are sent to a higher rank adder from a lower rank one. Further, a bypass carry line 31 is set between the carry input and the carry output in parallel with the line 15 and connected to a wired OR via the gates 21. Thus, a by pass is formed by the line 31 in case no carry is produced from those adders 3-5 and the carries produced at the lower rank side of the adder 1 are transmitted to the higher rank side of the adder 5.
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