发明名称 MEMORY CONTROL SYSTEM
摘要 PURPOSE:To enable plural decentralized processing parts to work independently of a main processing part and to improve the performance of a memory control system, by providing a single machine cycle between access cycles when the continuous accesses are given to the decentralized memory parts from the decentralized processing parts and accepting the access request in said idle cycle from the main processing part. CONSTITUTION:A single access cycle is defined as a 3-machine cycle and an idle 1-machine cycle is provided only when the access requests are given continuously from the decentralized processing parts 3. Then the acceptance of the next request is delayed by a single machine cycle under the control of the decentralized memory control parts 4. Thus the accesses given to the decentralized memory parts 5 from a main processing part 1 can be accepted in said idle cycle. Furthermore an access is possible synchronously with the action of the remote side. Thus the parts 3 can work independently of the requests of the part 1 and the performance of a memory control system is improved.
申请公布号 JPS63240662(A) 申请公布日期 1988.10.06
申请号 JP19870072986 申请日期 1987.03.28
申请人 HITACHI LTD 发明人 YONEZAWA MASASHI;YOSHIZAKI KATSUHIRO
分类号 G06F15/16;G06F13/16;G06F15/177 主分类号 G06F15/16
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