| 摘要 |
<p>A method for forming vertical metal interconnects on a semiconductor substrate having an uneven surface comprises first forming a laminated metal structure over the entire substrate. The laminated metal structure includes a first metallization sublayer, an intermediate etch stop barrier layer, and a second metallization sublayer. Usually, a barrier layer will be formed between the substrate and the laminated metal structure. The laminated metal structure is then patterned into the desired vertical metal interconnects, which interconnects are at different elevations because of the uneven underlying surface. The vertical metal interconnects are then planarized by first applying a dielectric layer and a sacrificial layer, etching back the combined dielectric and sacrificial layers to expose only the higher vertical metal interconnects, and then selectively etching back the second metal sublayer component of the higher vertical metal interconnects. By properly choosing the thicknesses of the various layers in the laminated metal structure, vertical metal interconnects having substantially identical elevations will be created.</p> |
