| 摘要 |
PURPOSE:To prevent the generation of miswriting by supplying an output signal from a latch circuit for holding the timing of a clock signal, a delay signal of the clock signal and the clock signal itself to a logic circuit at the timing changing the clock signal from the other level to one level and forming a write mode deciding signal. CONSTITUTION:When clock signals supplied from terminals CKH, CHL are changed from one level to the other level, a write enable signal supplied from a terminal WE is fetched. The output signal of the latch circuit FF for holding the timing changing the clock signal from the other level tone level, the delay signal of the clock signal and the clock signal itself are supplied to the logic circuit to form a write mode deciding signal. Since the output of the logic circuit is a signal forcedly indicating a read mode during a signal fetching period or until the output of a latch circuit FF is established.
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