| 摘要 |
PURPOSE:To prevent malfunction due to simultaneous change in an output buffer by providing a 1st stage logic gate, the next stage logic gate and a one-shot pulse generating circuit supplying a lock signal on an input of the next stage logic gate while being triggered by an output of the next stage logic gate. CONSTITUTION:The titled circuit consists of the 1st stage 2-input NOR gate 3, the next stage 2-input NOR gate 4 and the one-shot pulse generating circuit 5 receiving the output of the gate 4 as the input, generating a high level pulse signal at the trailing of an output signal 4 and whose output is given to the other input of the gate 4. When an internal chip select signal 2 and an external input signal 1 go to a low level, the output of the NOR gate 4 reaches a low level. In this case, the circuit 5 generates a high level pulse signal. Moreover, the output buffer 6 generates the data signal by the output signal of the gate 4. Even when the level of the input signal changes based on the fluctuation of a ground line or a power line 7, since the output of the circuit 5 keeps a high level, the output of the gate 4 is unchanged.
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