| 摘要 |
<p>The logic signals (S0, S1, S2, HL) which define the pixel are combined together with the synchronisation signals (HS, VS) by a composer circuit (19) disposed in the display control, to form a single composite signal. The composer circuit (19) is connected by way of a single conductor (21) to a separator circuit (29) for separating the synchronising signal, disposed in the VDU control circuit (20). The VDU control circuit comprises horizontal and vertical deflection circuits (27, 43 and 28, 44) for a CRT (24) and further comprises a format selector circuit (30) which is capable of sensing the duration of the vertical synchronising pulse to control the frequency of the video signal vertical deflection circuit (28, 44).</p> |
