发明名称 DYNAMIC TYPE RAM
摘要 PURPOSE:To offset a change due to masking deviation in coupling capacity between word lines and data lines, to suppress array noise and to improve a reading operation margin by connecting one and the other of memory cells using a drain area in common to divided word lines and word lines every same number or every approximately same number. CONSTITUTION:One or the other of memory cells using the drain area D in common of an address selecting MOSFET Qm are connected with the adjacent divided word lines every same number or every approximately same number by crossing the divided word lines DWLa1-DWLas+1, DWLb-DWLbs on the connection parts between the divided word lines DWLa1-DWLas+1, DWLb1-DWLbs and word lines WLa, WLb. Even if coupling capacity values cf1, cf2 on the drain connecting pads of the memory cells are changed by a masking deviation, the change of the coupling capacity observed from one divided word lines, i.e. the word lines WLa, WLb is offset and the coupling capacity between each data line DL and its adjacent word lines WLa, WLb has almost the same electrostatic capacity. Consequently, array noise can be suppressed and the reading margine can be improved.
申请公布号 JPS63239674(A) 申请公布日期 1988.10.05
申请号 JP19870071429 申请日期 1987.03.27
申请人 HITACHI LTD 发明人 KAJITANI KAZUHIKO;TSUCHIYA OSAMU
分类号 G11C11/401;G11C11/408;H01L21/8242;H01L23/522;H01L27/10;H01L27/108 主分类号 G11C11/401
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