| 摘要 |
PURPOSE:To stabilize serial data transferring operation by specifying the number of cycles of a clock signal up to the start of the transfer operation after starting the data transfer cycle to determined timing for starting the transfer operation of reading data to a data register. CONSTITUTION:The number of cycles of a serial clock signal SC from the start of the data transfer operation of reading data after starting a dual port memory is specified by binary display. These cycles are supplied to correspond ing bits of a counter circuit CTR in a timing control circuit TC as internal data io1-io4. The counter circuit CTR can optionally specify a clock signal position for starting the transfer operation in accordance with its count value and a counting-down counter circuit CTR built in the dual port memory can execute transfer operation synchronized with a clock signal. Consequently, the transfer operation of display data can be stabilized.
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