| 摘要 |
<p>A cache memory (50) consists of M partitions of independently addressed set associative memory in a single memory complex having N ports of access to the M partitions where N is less than or equal to M. Control means (54, 56) direct input addresses in a global fashion to all partitions or in a local fashion to a particular set of partitions specified as the output of PLATs (100, 102, ..., 108) which receive memory request addresses. The PLAT either hits and provides the desired partition identifier or misses and a global request of the cache memory (50) must occur. If a global request of all partitions of a cache memory (50) occurs and creates a hit, a new PLAT entry is created to identify the partition in which the desired information is stored.</p> |
