| 摘要 |
PURPOSE:To enable the formation of a high density programmable logic array, by laminating a plurality of wiring layers on a semiconductor substrate and connecting logic gate unit cells with an output stage logic gate cell via a first wiring layer and connecting the logic gate unit cells with input signal wires via a second wiring layer. CONSTITUTION:A plurality of basic cells are juxtaposed over the whole surface of a chip region of a semiconductor substrate so as to form logic gate unit cells 70-1-70-4 and an output stage logic gate cell 71. A plurality of wiring layers are further laminated on the semiconductor substrate, and the logic gate unit cells are connected with the output stage logic gate cell via a first wiring layer out of the wiring layers, and the logic gate unit cells are connected with input signal lines via a second wiring layer. A programmable logic array of a normal master structure having a high mounting density can be thus formed.
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