| 摘要 |
PURPOSE:To reduce the number of operation clocks by divisionally storing a conversion coefficient in two registers and processing multiplication and addition in parallel. CONSTITUTION:A 3X3 coefficient matrix M33 held in a first register and (x), (y), and (z) components of an input vector V=[x, y, z, 1] are multiplied. Multiplication results are accumulated for each of (x), (y), and (z) components, and elements of the fourth row held in a second register are added to them to obtain outputs of respective components x', y', and z' of an output vector, and a constant 1 is added to this output vector independently to obtain an output vector V'. Consequently, the operation related to a constant part in the conversion matrix is omitted or simplified to reduce the number of times of multiplication and addition, and multiplication and addition are processed in parallel. Thus, the number of operation clocks is reduced. |
