发明名称 DELAY CIRCUIT
摘要 <p>PURPOSE:To simplify a circuit, to save a space and to obtain a highly accurate delay time by arranging a 2nd wiring near a 1st wiring for transmitting the a signal and supplying a 2nd signal having the same phase or a reverse phase as/against the 1st signal to the 2nd wiring to change the transmission time of the a 1st signal by a mirror effect. CONSTITUTION:When a clock signal phi is inputted to an input terminal 30a of the 1st wiring 30 and a clock signal, the inverse of phi, having a reverse phase is inputted to an input terminal 31a of the 2nd wiring 31 through a pad 34 and a wire 32, coupling capacity between the 1st and 2nd wirings 30, 31 is set up to about 2CP by the mirror effect. When the clock signal phi having the same phase is inputted to the input terminal 31a of the 2nd wiring 31 through a pad 33 and the wire 32, the potential of the 2nd wiring 31 is set up to the same value as the 1st wiring 30 and the coupling capacity CP is reduced to a value which may be apparently neglected when observed from the 1st wiring 30. Thus, the delay time of the clock signal phi flowing in the 1st wiring 30 can be changed.</p>
申请公布号 JPS63238713(A) 申请公布日期 1988.10.04
申请号 JP19870072746 申请日期 1987.03.26
申请人 OKI ELECTRIC IND CO LTD 发明人 ENDO HIDEAKI
分类号 H03K5/13 主分类号 H03K5/13
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