| 摘要 |
<p>PURPOSE:To reproduce the amplitude and timing of a transmission signal and to cause the delay to be smaller by resetting a reception processing part and an output processing part with a resetting signal obtained by counting while a starting signal is received. CONSTITUTION:When an input transmission signal Di is received, a counter 2 starts the counting with the rise of a starting signal ST, a counting signal CN is coded by a decoder 3, sends a sample timing signal SP to an output processing part and generates a resetting signal RS. At an output processing part 4, the signal SP is received, the signal Di is sampled by the rise and a reproducing output Do is obtained. A reception processing part 1 to receive the signal RS turns off the signal ST, and the counter 2, since the signal ST falls, resets the counting signal. The decoder 3 stops the output of the signal RS by the resetting of the signal CN from the counter 2. By a series of actions, the transmission of one frame is completed, and the delay of the output Do to the signal Di comes to be a half bit only.</p> |
