| 摘要 |
<p>PURPOSE:To improve a system function as keeping a compatibility with an existing device by delivering and receiving data by selecting different clocks so as to match the function of other side. CONSTITUTION:Data processor 10, 20, 30 are connected by a bus 40, and the bus using right acquisition control parts of the respective processors are synchronizing with a low speed clock. The data processor 10 is capable of performing a transmission as synchronizing with both the low speed and the high speed clocks, but the data processors 20 and 30 are capable of performing the transmission as synchronizing with only the high speed and the low speed clock respectively. In the case of the transmission from the data processor 10, the bus using right acquisition control part 11, after acquiring a bus using right, transmits a transfer mode, made to match other side, to a data delivering receiving part 12 through a driver 13 and an invertor 15, and the data delivering receiving part 12 performs the transmission as synchronizing with the clock of other side. At the time of the reception at the data processor 10, the output of the driver 23 or 33 is transmitted to the data delivering/receiving part 12 through a transfer mode line 41, and it can receive it as synchronizing with the clock of other side.</p> |
