| 摘要 |
PURPOSE:To prevent the current in a test signal generation circuit from flowing by setting an RS flip-flop when an electric potential for testing is applied to an input terminal and an electric potential different from a fixed electric potential is applied to the source of a depletion transistor. CONSTITUTION:When a sufficiently lower level than ground (GND) level is applied to an input terminal 1, an N-type depletion 4 is turned off and when a level at input terminal 1 is further lowered the input level of an inverter 5 is brought to near the GND level. Since the gm of the P-type MOS transistor of the inverter 5 is greater in comparison with the N-type MOS transistor 4, if the input level is made lower than the level of power source voltage (VDD), an output is inverted and the output of the inverter 5 is set to the VDD level. This sets an RS flip-flip 7 and a test signal 6 set to the VDD level and activated.
|
