| 摘要 |
A process control circuit comprises a plant controller (I), an output signal controller (II), and a compensation circuit (III) for delay element of process including feedback circuit of the controller (II). The output (Vo) of disturbance (Up) feedbacked to the controller (I) is turned to time leading signal by R9-10 and C2. The values of R1-3, R7-9 and C2, C3 are adjusted to reduce the effect of the disturbance which means the transfer function of Vo(S)/Up(S) to be zero regardless of the transfer characteristic or delay time.
|
