发明名称 FREQUENCY SYNTHESIZER
摘要 PURPOSE:To prevent erroneous locking even when a VCO is oscillated at an image frequency by opening the loop of a PLL when the output signal of the VCO is an image frequency. CONSTITUTION:A comparator 15 compares a control signal VT and a reference signal VT of a VCO 1, and at the time of VT<VR, a comparator output voltage signal 17 of an L is outputted. Thus, a frequency signal f1' AND-executed by an AND gate 18 comes to zero. Then, f1'<fref (fref is the output frequency of a reference frequency transmitter 9 is obtained, and therefore, the signal VT is controlled so as to become gradually higher. As the result, the signal 17 comes to be H and f1'=f1 (f1 is a divided 7 frequency signal.) is obtained. The signal is converged so as to come to f1'=fref, stabilized and the lock condition is obtained. Thus, when the output frequency of the VCO 1 is an image frequency, the loop of the PLL is opened, the locking is not executed, and the VCO 1 is controlled so as to move to the inherently desired frequency.
申请公布号 JPS63234723(A) 申请公布日期 1988.09.30
申请号 JP19870069319 申请日期 1987.03.24
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 AOKI SHIGEO
分类号 H03L7/187;H03L7/18 主分类号 H03L7/187
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