发明名称 OUTPUT CIRCUIT IN MOS INTEGRATED CIRCUIT
摘要 PURPOSE:To increase the electrostatic breakdown strength of an output pin by constituting the circuit that a depletion type MOSFET is connected between the output pin and an output buffer to make a high voltage applicable to its gate. CONSTITUTION:MOSFETQ1, Q2 constituting an output stage 3a are turned on/ off complementarily. Further, a depletion MOSFETQ3 is connected between an output pad 5 and an output node n1 of the output buffer circuit 3. A gate terminal of the FETQ3 is connected to a power supply line and a power supply voltage VDD is applied thereto. When the FETQ3 is used in an LSI and a power supply voltage is applied to a power supply pin, the gate voltage is brought to a level of the voltage VDD and its resistance value is suppressed to a low value. Further, when no power supply voltage is applied to the LSI in the operation such as handling or the like, the gate voltage is brought to 0V and the resistance value of the FETQ3 is increased. As a result, the speed of the output circuit 3 at the operation as the LSI is reduced slightly and electrostatic breakdown is prevented at handling.
申请公布号 JPS59107634(A) 申请公布日期 1984.06.21
申请号 JP19820216922 申请日期 1982.12.13
申请人 HITACHI SEISAKUSHO KK;HITACHI MAIKURO COMPUTER ENGINEERING KK 发明人 SUZUKI YOSHITO;SHINAGAWA YUTAKA
分类号 H03K19/0944;H03K17/687;H03K19/003;H03K19/0175 主分类号 H03K19/0944
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