发明名称 INTEGRATED CIRCUIT TESTER
摘要 PURPOSE:To reduce the scale of a tester by providing a controller for transferring output data to a data analyzer at every storage of a prescribed number of the output data in a memory and outputting a starting signal to a pattern generator and the like when a comparative analysis is terminated. CONSTITUTION:When a pattern generator 21 is operated, (m)-bit parallel pattern signals determined in advance are inputted to the input terminals 2-1-2-m of an integrated circuit 1 to be measured. At this time, when the output terminal 3-1 of the circuit 1 is selected 22, series output data signals (a) (a1, a2...) are outputted from a selection circuit 22. The signals (a) are inputted to a converter 24 via an acquisition circuit 23 and changed over to a plurality of parallel lines in synchronism with clock signals to be outputted. Accordingly, data (a) are stored 25 as parallel data. Thus, when a prescribed number of the data (a) outputted from the terminal 3-1 are stored 25, a transfer signal is outputted from a controller 32 to a memory 25, stored 25 output data are stored 28 in the prescribed region of a data analyzer 27, compared 30 with reference data stored in a memory 29 and a comparison result is outputted.
申请公布号 JPS63233385(A) 申请公布日期 1988.09.29
申请号 JP19870067142 申请日期 1987.03.20
申请人 ANRITSU CORP 发明人 KAGAWA MITSUAKI
分类号 G01R31/28 主分类号 G01R31/28
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