| 摘要 |
PURPOSE:To reduce the number of terminals and to enlarge the capacity of a storage only by providing a simple external circuit by providing a logical circuit for outputting a signal for making a three state driver active at the time of inputting a prescribed logical signal to a data input line at the time of a reading operation. CONSTITUTION:At the time of reading the data, address data is applied to address lines A0-A9, the signal of a logical circuit level '1' is inputted to a reading and writing control line RW, the signals of the logical levels '0, 0, 1, 1' are respectively inputted as selecting signals to data input lines a-d. An AND gate 4 outputs the signal of the logical level '1' to make the three state driver 5 active and output the data of four bits read from a memory cell array 1 to data output lines D00-D03. Thereby, the selecting signal can be inputted from the data input lines a-d, a terminal for the selecting signal is not required and the memory having the large capacity of the storage using plural memory elements can be easily constituted without externally providing a complicate decode circuit.
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