| 摘要 |
PURPOSE:To keep the pulse width of the clock input of a D flip-flop to a level exceeding a constant value by using control signals from two asynchronous systems and to prevent the malfunction or the do-nothing operation of a D flip-flop for data transfer from being generated, by providing the D flip-flop, a first pulse generation circuit, and a second pulse generation circuit. CONSTITUTION:The titled circuit is constituted of the D flip-flop 1 and the first and the second pulse generation circuits 110 and 120. The first pulse generation circuit 110 is provided with a NAND gate 4, inverters 7-9, and a capacitor 11, and generates a pulse with the pulse width directing downward at an output terminal 111 by the leading edge of the control signal applied on an input terminal 101, and the second pulse generation circuit 120 is provided with a NOR gate 2, inverters 5 and 6, and a capacitor 10, and connects the output terminal 111 of the first pulse generation circuit 110 to the input terminal on one side of the NAND gate 3. And it generates the pulse with pulse width tw directing upward at an output terminal 122 by the trailing edge of the control signal applied on a control signal input terminal 102. Therefore, it is possible to perform the data transfer in spite of the timing of the control signal.
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