| 摘要 |
PURPOSE:To prevent the deterioration of performance due to a queuing state set when a cache memory is cleared by providing a boundary register to show the boundary between regions in a main storage device and comparing a main memory access address with the contents of the boundary register to set a region. CONSTITUTION:A boundary register 11 shows the boundary between a region used exclusively by an exclusive processor and another region within the main storage device. A boundary comparator 12 compares a main memory access address given from a requester with the contents of the register 11. When the result of this comparison shows the region which is exclusively used by an exclusive processor, the information on a cache control circuit 13 is stored into 1st storing means 21 and 23 or 2nd storing means 22 and 24 corresponding to the address arrays 14 and 15. Then the circuit 13 clears the storing means kept so far in a busy mode when a selective cache clear is requested and hereafter functions to select other storing means. Thus it is possible to prevent the deterioration of performance due to the queuing state set when a cache memory is cleared.
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