发明名称 MULTIPLE ADDRESS COMMUNICATION SYSTEM
摘要 PURPOSE:To contrive the improvements of the processing efficiency and the line utilizing efficiency by allowing an instruction requesting equipment to transmit an instruction simultaneously to plural instruction execution devices via a multiple address communication means so as to execute the processing in parallel. CONSTITUTION:The instruction requesting equipment 1 transmits an instruction to plural instruction execution device 2, 3, N via a multiple address communication means 10 by simultaneous multiple address communication and receives sequentially a reply from the instruction execution devices 2, 3, N completing the execution of the instruction by executing the polling requesting a reply to the instruction execution devices 2, 3, N according to a prescribed sequence. That is, the execution of parallel processing is realized by the plural instruction execution devices 2, 3, N in the transmission of the instruction by the simultaneous multiple address and sure reply having stable speed is obtained by retransmitting the instruction by the instruction unreception reply and the request of the reply by the polling. Moreover, as to the reception and processing of the reply by the instruction requesting equipment 1, since it is executed serially by the polling, the possibility of the reception of plural replies at the same time is precluded. Thus, high processing efficiency and line utilizing efficiency are attained with the stable reply speed.
申请公布号 JPS63234646(A) 申请公布日期 1988.09.29
申请号 JP19870068432 申请日期 1987.03.23
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YOSHIMURA HIDEKO;OKAMURA YOSHIMI;UEDA KENICHI
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