| 摘要 |
PURPOSE:To obtain a stable phase locked output by supplying a free-run output of a count means to a phase comparator circuit in place of an input signal whose pulse width is widened if the pulse width of the input signal is partially wider than the pulse width of a signal in a normal frequency range. CONSTITUTION:If the pulse width of the input signal is wider than the range of the normal pulse width at which the phase locking is taken in the phase locked loop, on L level pulse signal is generated from a NAND circuit 20 and a counter 21 generates an output signal at its free-run frequency. In this case, since the free-run frequency of the counter 21 is set slightly lower than the normal frequency of the input signal, the phase locked loop can sufficiently continue the phase locking. Since the output signal with the free-ran frequency of the counter 21 is given to the phase comparator circuit 12 in place of the input signal, the phase locked loop keeps the phase lock state. Thus, a stable phase locked output is obtained. |
