| 摘要 |
<p>PURPOSE:To omit a labor and time to constitute a pulse generation circuit at every case corresponding to a request, by generating a signal delayed in order, and performing the arithmetic operation of a logical product of inputs mutually and the arithmetic operation of a logical sum of arithmetic results by a program in addition to a composite programmable logical element PLA with a various kinds of frequency dividing signals. CONSTITUTION:A frequency dividing means 101 generates a signal in which the signal of original oscillation frequency is frequency2<n>(n=0, l, 2,...)-divided. A selector 102 selects and outputs either the frequency divided outputs of the frequency dividing means 101. A delay means 103 outputs signals delayed by different times from the output signals of the selector 102 to respective tap. The composite programmable logical element 104 receives the output of the frequency dividing means 101 and the tap output of the delay means 103, and executes the arithmetic operation of the logical product of arbitrary combination between input signals mutually and the arithmetic operation of the logical sum between the output signals of the arithmetic results by the program. In such a way, it is possible to omit the labor and time to constitute the pulse generation circuit at every case corresponding to the request, and to respond to the change of specification, etc., flexibly.</p> |
