发明名称 FRAME SYNCHRONIZATION PROTECTION CIRCUIT
摘要 <p>PURPOSE:To attain backward protection by a count of counters of the number of stages equal to the backward protection stage number by inputting a detection output of a frame pattern detection circuit to a reset terminal not only to a set terminal of an SR flip-flop of an alarm control circuit. CONSTITUTION:If a frame pattern detection circuit 1 does not detect a frame pattern synchronously with a 1st decoding signal H1 but detects at the next point of time at the point of time of the first frame pattern detection after the occurrence of alarm, an output D of an alarm control circuit 3 goes to 1 and an output C of the reset signal generator resets it to zero. During this time, the clock CLK of the frame counter 7 is not inhibited and 0 is fetched in the alarm counter 4. In detecting the frame pattern by the pattern detection circuit 1 in synchronism with 0 of the 1st decoding signal H1 at the point of time of the detection of next pattern, the alarm counter 4 fetches and counts 1 being the conversion of output D to apply normal operation.</p>
申请公布号 JPS63232652(A) 申请公布日期 1988.09.28
申请号 JP19870066011 申请日期 1987.03.20
申请人 FUJITSU LTD 发明人 IKUMA HIROSHI
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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