发明名称 SIGNAL SYNTHESIZING CIRCUIT
摘要 PURPOSE:To supress the generation of a jitter accompanying the time base change of an A/D converter by arranging the inclination characteristics of each LRF connected to the front step of the A/D converter in the synthesizing circuit of a video signal and an external input character signal. CONSTITUTION: V2= V1/2 is held between a maximam level V1 of a synthesizing signal YS0 to add a composite video signal inputted into LPFs 26, 27, a YS signal and a YM signal and a maximam level V2 of the luminance and color-difference signals Y2, U2, V2 of the external input character signal inputted into LPFs 28-30. The LPF27 and the LPF28 are set so that rise characteristics in respective output signals YS0' and Y2' can be equal, namely V1/ t1='V2/ t2. Thus, when the time base of the sampling clock of A/D converters 7-10 is changed, a jitter to occur at the output signal comes to be equal. Consequently, when subtracting and adding are executed by subtracters 12-14 and adders 15-17, the jitter can be canceled.
申请公布号 JPS63232759(A) 申请公布日期 1988.09.28
申请号 JP19870066432 申请日期 1987.03.20
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 IKUHARA HIDEYUKI;OKUMURA NAOJI
分类号 H04N5/278 主分类号 H04N5/278
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