发明名称 FRAME SYNCHRONIZATION CONTROL SYSTEM
摘要 <p>PURPOSE:To immediately cope with frame out of synchronism by detecting the destruction of the regularity of the internal state of a maximum likelihood decoding means so as to find out frame out of synchronism surely. CONSTITUTION:A reception signal is sent to a maximum likelihood transmission data series estimate means 14 of a Viterbi decoding means 13. An enable state transition specification means 16 of a maximum transmission data series estimate means 14 specifies the enabled state transition based on the reception signal and a signal point data. If frame out of synchronism takes place, in applying decoding by the Viterbi decoding means 13, a minimum branch metric for each node and a difference between path metrics at each node stored in each stage of an internal bus memory 24 obtained from the branch metric are almost eliminated to uniformize the path metric. Thus, an irregularity detection signal is outputted as the occurrence of out of frame synchronism.</p>
申请公布号 JPS63232650(A) 申请公布日期 1988.09.28
申请号 JP19870066075 申请日期 1987.03.20
申请人 FUJITSU LTD 发明人 OCHIAI TAKANAO
分类号 H04J3/00;H03M13/33;H03M13/41;H04B1/76;H04L7/00 主分类号 H04J3/00
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