| 摘要 |
PURPOSE:To convert stably data at a high speed by ANDing a clock signal of 4-series parallel data and a 2-multiple clock signal by a 1st 2-multiple means by means of an AND means so as to use the signal as a trigger pulse of a 4-bit shift register. CONSTITUTION:The 4-series parallel data shown in figure (a) fed to signal input terminals 1A-1D are ANDed with a timing signal of 4-series being an output signal of a shift register 3 by AND gates 2A-2D. A clock signal of a parallel data shown in figure (b) fed to a clock input terminal 4 and a signal shown in figure (c) being 2-multiple of the signal by a clock 2-multiple circuit 5A are used and ANDed by an AND gate 6 to obtain a signal shown in figure (d) from the timing signal. Then the result is used as a trigger pulse and inputted to the shift register 3 to give a 4-bit circulating function. Thus, even with a high speed shift register without any circulating function in use, the 4-series parallel data of 16QAM system is converted into a serial data of one series stably at a high speed with simple circuit constitution. |
