| 摘要 |
<p>A nonvolatile semiconductor memory device having a bit-line potential amplifying circuit (2) for amplifying the data potential read from a selected one of memory cells (MC) and a dummy bit-line potential amplifying circuit (6) for amplifying the data potential read from a dummy cell (DC). These amplifying circuits (2, 6) are of the same structure. The bit-line potential amplifying circuit (2) comprises a first MOS transistor (Q1) of N-channel type for clamping the bit-line potential, a second MOS transistor (Q3) of the N-channel type for amplifying the bit-line potential, and a third MOS transistor (Q2) of an N-channel type functioning as a load of the second MOS transistor (Q3). The dummy bit-line potential amplifying circuit (6) comprises a fourth MOS transistor (Q12) of the N-channel type for clamping the dummy bit-line potential, a fifth MOS transistor (Q14) of the N-channel type for amplifying the dummy bit-line potential, and a sixth MOS transistor (Q13) of the P-channel type functioning as a load of the fifth MOS transistor (Q14). The fifth MOS transistor (Q14) has the same element size as the second MOS transistor (Q3), and the sixth MOS transistor (Q13) has the same element size as the third MOS transistor (Q2). In addition, the fourth MOS transistor (Q12) is driven by a current more readily than the first MOS transistor (Q1).</p> |
