| 摘要 |
PURPOSE:To reduce the number of signal lines by making any of a data signal line, a clock signal line and a strobe signal line common. CONSTITUTION:The data signal line 23 and the clock signal line 25 are made common in a first frequency synthesizer and a second frequency synthesizer 3. A data signal is inputted in shift registers 19a and 19b and when a strobe signal STB1 becomes ON in the first synthesizer 1 the contents of the register 19a is transmitted to a latch circuit 21a and the number of division of a variable divider 17a is altered so as to set the frequency of the first synthesizer 1. In this case, the data signal is also transmitted to the shift register 19b, but the number of division of the variable divider 17b is not altered as far as the strobe signal STB2 does not become ON. Thus, the number of signal lines can be reduced since the data signal line 23 and the clock signal line 25 are made common.
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