| 摘要 |
<p>PURPOSE:To simplify a frame synchronizing circuit by extracting input data with frame synchronization take while using a prescribed low-speed clock from an input data string and inserting it to an elastic store. CONSTITUTION:An input-side synchronizing information circuit 5 receives a detection output FL of a synchronizing detection circuit 4 and generates 4-bit pulse representing synchronizing information SL at each 252 bits of 1.5M data input, and outputted as a low-speed 256-bit data DL inserted to the time slot of 4 idle data in an input-side data extraction/insertion circuit 2a. An output-side synchronizing information extraction circuit 6 extracts 4-pulse signal sH corresponding to the input-side synchronizing information sL from a high-speed 256-bit data DII outputted from the 256-bit elastic store 1. The output-side data extraction/insertion circuit 2b uses a timing signal tH and a 8.192Mb.s clock fH to collect the 256 bit data DH outputted from the 256-bit elastic store 1 in 4 units each, 1024-bit is takes as one frame and the said 1024-bit data is sent extenally while frame synchronization is taken at a period of 125mus in 8 kHz. Since the synchronizing detection circuit of the output side is saved in this way, the circuit is simplified.</p> |
