发明名称 TEST CIRCUIT COMPOSED OF COMPLEMENTARY MOS TRANSISTOR
摘要 PURPOSE:To eliminate current consumption even when a potential is applied to an input terminal by adding a 1st p channel transistor (p-ch Tr) between 3rd and 4th n-ch Trs and controlling its gate. CONSTITUTION:When a potential VDD+2V is applied to the input terminal and a stop signal 107 which is the gate signal of the 1st p-ch Tr 105 is at the GND potential, a point 111 is set at a 1st potential between the GND potential and a potential VDD determined by the on resistance ratio of the 3rd n-ch Tr 104, 1st p-ch Tr 105, and 4th n-ch Tr 106, and the potential VDD with which a test signal 110 is active is outputted. Further, when the potential VDD is applied to the input terminal 101 and the current consumption needs to be reduced, the stop signal 107 is set to the potential VDD and then the potential 111 is held at the GND potential, so that the test signal 110 is held at the GND potential and made nonactive.
申请公布号 JPS63231278(A) 申请公布日期 1988.09.27
申请号 JP19870066579 申请日期 1987.03.19
申请人 NEC CORP 发明人 KOGA TAKATOSHI
分类号 G01R31/317;G01R31/28;H03K17/687 主分类号 G01R31/317
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