发明名称 BIT SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To enable data reproduction in fast-forward mode by switching the characteristics of a phase-locked loop circuit which extracts reproduced data and performs bit synchronization to characteristics with a wide capture range when a fast-forward reproducing means is put in operation. CONSTITUTION:Signals reproduced by heads 2A and 2B are applied to a playback amplifier 13 through a switch 12 at the time of reproduction and then applied to a bit synchronizing circuit 15 through a waveform shaping circuit 14. The output data and clock of the circuit 15 are supplied to a reproduction processing circuit 16. The circuit 15 inputs data by an FF 100 and a clock is generated by a PLL circuit which compares the data of the circuit 14 with the clock of a voltage-controlled oscillator 10. In normal play mode, a transistor (TR) 108 is turned on with outputs 21F and 21R of a microcomputer 21. In fast search mode, the TR 108 is turned off and the characteristics of the PLL circuit are switched to the characteristics with the wide capture range. Thus, the circuit is put in operation with characteristics with a good error rate in normal play mode and data reproduction can be performed even in fast search mode.
申请公布号 JPS63231769(A) 申请公布日期 1988.09.27
申请号 JP19870063701 申请日期 1987.03.20
申请人 HITACHI LTD 发明人 TAKEUCHI TOSHIFUMI;ARAI TAKAO;AMADA NOBUTAKA
分类号 G11B20/14;H03L7/10;H03L7/107 主分类号 G11B20/14
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