| 摘要 |
PURPOSE:To omit the increment of the number of terminals for an LSI processor by adding an information transfer circuit to control connection between many I/O lines and the I/O lines of the LSI processor. CONSTITUTION:At the time of recognizing the transmission of a transfer request signal from a block to an information transfer request input signal terminal Ti2, a processor body 2 sends data to be transmitted and a control signal respectively to a writing information line 301 and a control line 302 and stores data in a register 13. Then, the processor body 9 sets up a flip flop (FF) 19 through a transfer data receiving line 600. Said status is sent to an information transfer request output signal terminal T02, an AND circuit 10 and a tray state buffer 15 are driven and the transmission data are sent only to a data output terminal D02. After the end of transmission, the processor body 2 resets the FF 19 through a reset control line 601 and informs said reset to the opposite processor through the terminal T02. |
