| 摘要 |
PURPOSE:To increase the processing speed by executing the merging operation, where a storage area where plural data strings each of which includes p-number of records are arranged in the address order and a storage area where plural data strings each of which includes q-number of records are arranged in the address order are coupled, with one instruction from a processor. CONSTITUTION:With respect to the merging operation, records are read out from storage areas 5A and 5B one by one from their start addresses in accordance with the indication of a merge control circuit 3 by a data merging circuit 9. The data merging circuit 9 compares keywords and successively writes records in storage areas 6C and 6D in accordance with the keyword order designated by a data merging instruction 8. As the result, data strings 7 each of which includes (p+q)-number of records and which are arranged in the keyword order are completed in storage areas 6C and 6D. The output of the data merging circuit 9 is switched each time when merging of one data string is completed, and merged data strings are alternately stored in storage areas 6C and 6D. |
