发明名称 TEST METHOD FOR MULTI-PORT RAM
摘要 PURPOSE:To ensure a sure test for multi-port RAM by changing the position values of (n) pieces of bits of an address register for each port. CONSTITUTION:When the value of the lowest order bit of an address register 1-0 in a port 0 is set at 0, the address 0, 2, 4- are allocated to the side of the port 0. When the lowest order bit of an address register 1-1 is fixed at 1, the addresses 1, 3, 5- are allocated to the side of the port 1. Under such conditions, the tests are started at both ports 0 and 1. Thus different test patterns are given from both ports for each port with bits kept fixed. As a result, even the interference occurring between bits can also be checked on a memory plane.
申请公布号 JPS63229549(A) 申请公布日期 1988.09.26
申请号 JP19870065231 申请日期 1987.03.18
申请人 FUJITSU LTD 发明人 NAKAMURA KAN;ISODA YUTAKA;FURUYA KAZUHIRO
分类号 G06F12/16;G11C29/00;G11C29/56 主分类号 G06F12/16
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