| 摘要 |
PURPOSE:To prevent the operation speed from decelerating by a method wherein the substrate potential of MOS type transfer gate transistor is raised in case of accumulating data to lower the sub-threshold value leakage current while the substrate potential is lowered in case of a reading/writing process. CONSTITUTION:P wells 12 in the line direction on an n type Si substrate are split by SiO2 layers 13 into memory cells 14. Transfer electrodes and word lines 16 are provided on the regions between capacity electrodes 15, n<-> layers 18 and n<+> layers 19 on the regions 14 using polySi 16. The surface is covered with an SiO2 film 20 and openings 21 are made to provide Al bit lines 17 for connection to pick up layers of P wells 12. The P wells 12 connected to Al wirings 23 through the intermediary of the holes 22 are supplied with the substrate potential. In case of reading/writing process, the P wells in the selected line are supplied with a low substrate potential while in case of accumulating data, the P wells in the selected line are supplied with high substrate potential. Through these procedures, the charge accumulated in capacitors shall not leak through the intermediary of a transfer gate transistor not to erase the data. |
