发明名称 ADDRESS CONVERSION SYSTEM
摘要 PURPOSE:To prevent deterioration in the performance of an information processor in TLB trouble by adding the value corresponding to the instruction length of a real address by an adder when a real display bit indicates the real address, and setting it as the next real address in an instruction counter. CONSTITUTION:When an address commanded to an IC11 is a logical address, the off signal of the real display bit 21 is sent to a control circuit to cause an interruption to a microprogram under its control, and the found real address is set in the IC11 to turn on the real display bit 21. Then, when an advance of the program is made continuously, an ADD13 adds the instruction length to the contents of the IC11 and the result is set as the next address in the IC11. When the contents of the IC11 increases by said addition up to the next page, a carry signal is supplied to the digit indicating the page of the ADD13, so an OR gate 23 receives the signal to output a page cross signal. Thus, an MS/BS14 is read out by the real address and the processing of the information processor is performed by the read instruction.
申请公布号 JPS59110088(A) 申请公布日期 1984.06.25
申请号 JP19820218418 申请日期 1982.12.15
申请人 FUJITSU KK 发明人 SAKAI TAKASHI
分类号 G06F12/16;G06F12/10;G06F13/00 主分类号 G06F12/16
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