| 摘要 |
PURPOSE:To perform at a high speed such a process that must assure access sequence properties by suppressing the supply of address information to the holding means for address information in case it is decided that the address information are held by all holding means. CONSTITUTION:When an address (d)10111 is received from an address register 1, a request is sent to a buffer part 6 since two lower order bits of the address (d)10111 are equal to value 11. Then an address (e)10100 is sent from the register 1 and therefore a request is given to a buffer part 3 since two lower rank bits of the address (e)10100 is equal to value 00. In this case, the valid addresses are held by all entries of an address buffer 31 and therefore a request number counter 34 is equal to value 111. Thus a check circuit 36 sends value 1 to a control circuit 2 via a signal line 301 and the circuit 2 gives no request to the register 1 for transmission of an address. Hereafter the transmission of the address (e)10100 is held until an idle entry is secured in the buffer 31.
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