发明名称 BUS CONTROL SYSTEM
摘要 PURPOSE:To connect control adapters of various kinds to difference system buses by arranging and accessing first address spaces which are set in the control adapter in a memory space, converting address data on the buses based on a selection signal which is outputted by discriminating the first address and accessing the adapter. CONSTITUTION:The first address spaces 62 which are set in various registers which the control adapter 7 has are arranged in prescribed second address spaces 63 on a memory space 61, and the second address spaces 63 are addressed, whereby the control adapter 7 is accessed by a memory collation instruction. If the second address spaces 63 are addressed, address data outputted on a system bus 100 is converted into the first address space 62 based on the selection signal 50 which has detected said address spaces 63 and which has been outputted. Thus, the adapter which has been allotted to the spaces except for the address space to which a processor 1 cannot access and ten space 60 can be connected to the bus so as to execute access.
申请公布号 JPS63228358(A) 申请公布日期 1988.09.22
申请号 JP19870063034 申请日期 1987.03.18
申请人 FUJITSU LTD 发明人 SASAZAKI ISAO;HASHIMOTO SHIGERU;MATSUZAKI YUJI;MITSUISHI KAZUYUKI;IHI TOSHIAKI
分类号 G06F13/14 主分类号 G06F13/14
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