| 摘要 |
<p>A high-speed floating point arithmetic unit for microprogram-controlled arithmetic and comparation/logic operations, comprising a decoder (2) for various status signals including one indicating the generation of error in the arithmetic section (1), and a selector (4) for selecting one of the outputs of the decoder (2) based on microprogram control. In a stage preceding the selector (4) there is further provided an error memory (3) for storing information about the presence of an error during a series of operations, said information corresponding to each of the error-involving outputs from the decoder (2).</p> |
