| 摘要 |
PURPOSE:To shorten a cycle time by providing respective control signals for reading, writing, acknowledging and the like, permitting respective control signals to write from the other I/O and the like at the time of reading from either of I/Os and enabling these operation in the same read cycle. CONSTITUTION:While the I/O on the side of transmission or a memory 33 is read and data is transmitted on a data bus, the I/O or the memory on the side of reception can receive the data. When data is read from either of the I/Os 34 and 35 by the read control signal and data is written into the other I/O and the like by the write control signal WRITE, read and write control signals READ1 and WRITE1 which are different from the read and write control signals are generated from a DMA controller 32 and writing into other side is executed in the read cycle. Thus, the reading and the writing can be executed in the same cycle. |
