| 摘要 |
PURPOSE:To curtail the number of circuit element, and to reduce the chip area by allowing plural pulse width modulating circuits to share a combination of one frequency division counter and one coincidence circuit, and switching the modulating circuits by a switching circuit. CONSTITUTION:In accordance with a logical output (a) of the lowest bit of a frequency division counter 1, switching circuits 7, 8 are controlled, and one of data buffers 2, 3 and one of 1 bit latches 5, 6 are selected, respectively. In this case, the circuit 7 is constituted of tri-state buffers 7A-7F and an inverter 7G, and the circuit 8 is constituted of AND gates 8A, 8B and an inverter 8C. Also, the upper bits (b)-(d) of the counter 1 are compared with an output of the buffer 2 or 3 selected by the circuit 7 by using a coincidence circuit 4. In this case, the circuit 4 is constituted of EXNOR gates 4A-4C, a NAND gate 4D and an inverter 4E. As a result of this comparison, when a data coincidence has been detected, the 1 bit latch 5 or 6 is reset by an output (h) of the inverter 4E.
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