| 摘要 |
PURPOSE:To execute MR decoding at a high speed by setting the contents of a counter to an address register at the time of starting the decoding of one line, and also, counting the number of continuous image data of a decoding line. CONSTITUTION:An MR decoder 103 receiving an MH code of a head line and decodes an image, and delivers it to a DMA controller 101. The controller 101 writes successively the decoded image of the head line in an image memory, and also, delivers it to a counter 105. The counter 105 adds '1', if an image of one block of the line is all white, and also, a value of a flag register 106 is '0'. Subsequently, a reference line and a decoding line are decoded by an MR system. First of all, a value of the counter 105 is written in an address register 104, and also, delivered to a veriation point detector 102. The controller 101 delivers an image of the reference line to the detector 102 from a block of the number shown by the register. The detector 102 detects a variation point from the image of the reference line and derives a variation point address, and delivers it to the decoder 103.
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